Computer graphics workstations can provide highly detailed graphics simulations for a variety of applications. Engineers and designers working in the computer aided design (CAD) and computer aided manufacturing (CAM) areas typically utilize graphics simulations for a variety of computational tasks. The computer graphics workstation industry has thus been driven to provide more powerful computer graphics workstations which can perform graphics simulations quickly and with increased detail.
Modern workstations having graphics capabilities generally utilize "window" systems to organize graphics manipulations. As the industry has been driven to provide faster and more detailed graphics capabilities, computer workstation engineers have tried to design high performance, multiple window systems which maintain a high degree of use interactivity with the graphics workstation.
A primary function of window systems in such graphics systems is to provide the user with simultaneous access to multiple processes on the workstation. Each of these processes provides an interface to the user through its own area onto the workstation display. The overall result for the user is an increase in productivity since the user can then manage more than one task at a time with multiple windows displaying multiple processes on the workstation.
In graphics systems, some scheme must be implemented to "render" or draw graphics primitives to the system's screen. "Graphics primitives" are a basic component of a graphics picture, such as a polygon, vector or spline. All graphics pictures are formed with combinations of these graphics primitives. Many schemes may be utilized to perform graphics primitives rendering.
The graphics rendering procedure generally takes place within a piece of graphics rendering hardware called a scan converter. The scan converter manipulates graphics primitives and converts them into picture elements or "pixels" for storage in a "frame buffer" memory. A frame buffer generally comprises a plurality of video random access memory (VRAM) computer chips which store information concerning pixel activation on the system's display screen corresponding to the particular graphics primitives which will be traced out on the screen. Generally, the frame buffer contains all of the pixel activation data, and stores this information so that the graphics system can trace this information on the workstation's screen. The frame buffer is generally dynamic and is periodically refreshed.
Thus, computer graphics systems convert image representations stored in the computer's memory to image representations which are easily understood by humans. The image representations are typically displayed on a cathode ray tube (CRT) device that is divided into arrays of pixel elements which can be stimulated to emit a range of colored light. The particular color of light that a pixel emits is called its "value." Display devices such as CRTs typically stimulate pixels sequentially in some regular order, such as left to right and top to bottom, and repeat the sequence 50 to 70 times a second to keep the screen refreshed. Thus, some mechanism is required to retain a pixel's value between the times that this value is used to stimulate the display. The frame buffer is typically used to provide this "refresh" function.
Since frame buffers are usually implemented as arrays of VRAMs, they are "bit mapped" such that pixel locations on a display device are assigned x,y coordinates on the frame buffer. A single VRAM device rarely has enough storage location to completely store all the x,y coordinates corresponding to pixel locations for the entire image on a display device, and therefore multiple VRAMs are generally used. The particular mapping algorithm used is a function of various factors, such as what particular VRAMs are available, how quickly the VRAM can be accessed compared to how quickly pixels can be rendered, how much hardware it takes to support a particular mapping, and other factors.
In high performance computer workstation systems, it is generally desirable to access as many pixels simultaneously as is practical. However, to access as many pixels simultaneously as possible implies that each VRAM cycle accesses all VRAMs. It generally desirable to provide rendered pixel data for all VRAMs. Furthermore, high-density VRAMs are generally much slower than the hardware that renders pixels. There is therefore a long-felt need in the art for computer graphics renderers and frame buffers which allow simultaneous access to as many pixels as are needed to render an image, thereby reducing the number of accesses required to the frame buffer to completely render the image and decreasing the time it takes to ultimately write a graphics primitive to the system's screen.
Typical CRT devices for use with graphics workstations are "raster scan" display devices. Typical raster scan display devices generate images comprising a multiplicity of parallel, non-overlapping bands of pixels comprising sets of parallel lines. An example of such a system is disclosed in U.S. Pat. No. 4,695,772, Lau et al. The raster scan device disclosed in the Lau et al. patent is organized as an array of tiles. See Lau et al, col. 2, line 36. Raster scan devices generally utilize a multiplicity of beams for the red, green and blue (RGB) channels in the CRT. The multiplicity of beams generally write from the left side of the display CRT to the right side of the display CRT.
Typically, rendering algorithms calculate consecutive pixel values for consecutive pixels with small changes in their x,y addresses from pixel to pixel. This means that there is a large degree of "coherency" in the pixel addresses. When arranging VRAMs for simultaneous pixel access, it is desirable that the pixels that are accessed are allowed to be highly coherent.
Prior rendering schemes to generate pixel values sequentially generate all the pixels that make up a primitive, such as a polygon. Each primitive that comprises an image representation is used sequentially to generate pixel values. Therefore, a group of pixel values is generated which is stored in the frame buffer VRAMs. The x,y addresses of at least one of the pixels of a primitive is used to determine what row and column address should be applied to the VRAMs. Then, all the pixels in the groups so generated can be stored in a tile stored in the appropriate VRAMs. However, not all pixels in the group are accessible with a first tile access, and therefore additional tiles must be accessed from the frame buffer in order for the system to write a primitive to a CRT.
Certain prior graphics pipeline systems may utilize a "pixel cache" which functions as an intermediate storage memory for pixel data which will be written to the frame buffer. The pixel cache generally also connects the frame buffer to the rest of the graphics pipeline system and may, in certain instances, provide certain low level rendering procedures before writing the data to a frame buffer. Prior pixel caches in computer graphics systems typically are not utilized to provide high level processing of pixel data, but merely function as a temporary storage unit for data that is read out of the frame buffer VRAMs. An example of graphics system utilizing a pixel cache is the TURBO SRX graphics system provided by the Hewlett Packard Graphics Technology division, Fort Collins, Colo.
There is a long-felt need in the art for an intermediate pixel cache storage memory which can provide high level processing of pixel value data corresponding to graphics primitives. Such a pixel cache has not heretofore been provided in the computer graphics art. The inventors of the subject matter herein claimed and disclosed have invented novel pixel cache devices and methods which greatly enhance the speed at which graphics rendering to the frame buffer is accomplished, and which also greatly enhance rendering efficiency.